Principal R&D Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

We are seeking an experienced, highly motivated, and high-caliber individual to join our team as an R&D Engineer in Austin, TX. You are a visionary with a strong technical background in system frontend architecture, high bandwidth peripherals & protocols, timing, post-silicon characterization, and DFx domains. You have a proven track record of working on complex projects and delivering innovative solutions. Your ability to understand business priorities and translate them into technical tasks is exceptional. You thrive in collaborative environments and possess excellent communication and interpersonal skills, enabling you to work effectively with both internal teams and external customers. Your extensive experience in optimizing performance, power, and area (PPA) and improving execution schedules sets you apart. You are passionate about continuous learning and staying ahead of industry trends, always looking for opportunities to enhance existing products and create technical roadmaps for future innovations.

• Work on architecture & IP development projects
• Understand business priorities and break them down into technical tasks
• Identify enhancement opportunities and cost optimizations for existing products
• Develop novel ways to access on-chip Test, Debug & SLM data via high bandwidth and cost-efficient solutions
• Deploy new solutions into test chips and post-silicon characterization
• Create technical roadmaps for IP development

• Enable High-bandwidth test & SLM access with Semiconductor and ATE industry partners
• Enable fast integration of intelligent in-chip sensors and analytics
• Optimize performance, power, area, schedule, and yield of semiconductor products
• Enhance reliability of technology products across various applications
• Contribute to the development of differentiated products with reduced risk
• Drive continuous innovation in the SLM Hardware product portfolio
• Support Synopsys' leadership in chip design and verification

• BS or MS degree in Electrical Engineering with 15+ years of relevant industry experience
• Strong knowledge of Frontend Architecture and Digital design
• Hands-on expertise in high bandwidth protocols like USB, PCIE, and Ethernet
• Experience in optimizing PPA achieved pre-silicon and realized post-silicon
• Proven ability to improve execution schedules

• Possess strong system-design and microarchitecture skills
• Hands-on experience with HSIO protocols like PCIE and USB
• Experience with light weight CPU or microcontroller designs
• Knowledge of DMA concepts and DMA IP designs
• Familiarity with AXI and advanced AMBA/on-chip bus protocols
• Experience in DFT/DFx technologies and Scan, ATPG, BIST concepts is a strong plus
• Strong RTL design and coding experience in Verilog, System Verilog, VHDL
• Demonstrated expertise in productization of advanced technologies
• Exposure to prototyping new technologies via FPGA prototyping and/or Emulation

You will be part of the rapidly expanding Hardware-Analytics and Test (HAT) group, working on the development of Debug, Monitoring and Access solutions within the SLM Hardware product portfolio. This team is dedicated to addressing the increasing demand for test and monitoring data collection per chip, ensuring scalability and commercial viability of data access solutions. Collaborate with a talented group of professionals focused on innovation and excellence in semiconductor lifecycle management.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#LI-DP1