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DFD (Design for Debug) RTL Execution Lead

Microsoft
United States, Oregon, Hillsboro
Jul 16, 2025
OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a DFD (Design for Debug) RTL Execution Lead to join the team.
ResponsibilitiesDefine the micro-architectural implementation spec for debug IP's, fabrics & implement the micro-architectural specification in Verilog or System Verilog.Lead a team of engineers for IP & product DFD deliverables and support individual contributors in their own career growth.Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (system architects, front-end & back-end design verification, and post-si validation folks) with respect and with One Microsoft mentality to establish synergies.Refine Debug execution methodology and use of industry/home-grown tools to ensure design quality, effectiveness & speed up execution.Hold a primary role in enabling silicon by working directly with validation & fleet engineers to bring up debug capabilities and to help with diagnostics & screening.Work closely on Debug tool POC & roadmap associated with the RTL features implemented in design.Assess and then refine the implementation for debug coverage, area, power and performance. Ensure quality with checks covering Lint, CDC, Low Power intent and more.Delight your customers by delivering cutting-edge debug IP's & infrastructure for custom SoC designs that can perform complex and high-performance functions. Challenge the status quo with growth mindset.
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