New 
Senior Design For Test Engineer
 Microsoft | |
 United States, California, Santa Clara | |
 Jul 17, 2025 | |
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OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex SoCs and to join our team. It's a great opportunity to gain exposure all the way from DFT architecture to post silicon bring up. The candidate will design, implement, and validate scan, BIST, boundary scan and IJTAG features in our SoCs. Candidate will work closely with cross functional teams to generate and validate production vectors and work on silicon bring up. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
ResponsibilitiesBoundary scan insertion and validationMBIST insertion and validation including shared bus MBIST architectureEDT, SSN, and logic bist insertion and validationATPG pattern generation and validation for various fault modelsTiming constraint development for DFT structuresDesign and integrate test structures such as fuse, repair and on chip clocking controllersEmbody our culture and values. | |