Sr. Staff Design Verification Engineer

THE ROLE:

AMD is seeking a highly motivated Senior Staff Silicon Design Engineer to join our Silicon Design Engineering organization and contribute to the development of next-generation high-performance computing, AI, and graphics products. In this role, you will be a key contributor to the front-end design and DFT methodology team, driving design-for-test architecture, implementation, and silicon validation across complex SoCs.

You will collaborate closely with architecture, design, verification, physical design, product engineering, and manufacturing teams to ensure robust testability, high-quality silicon execution, and first-pass silicon success. This role offers the opportunity to influence DFT strategy and methodology while helping deliver industry-leading products to market.

THE PERSON:

The ideal candidate is a seasoned silicon engineer with strong expertise in Design-for-Test (DFT) architecture, implementation, and bring-up for complex semiconductor devices. You are a technical leader who thrives in a highly collaborative environment and can drive cross-functional efforts spanning design, verification, physical implementation, and product engineering.

You possess excellent analytical and problem-solving skills, demonstrate attention to detail, and are comfortable owning critical technical deliverables throughout the product lifecycle. You have a track record of independently driving complex projects, mentoring junior engineers, and influencing technical decisions across teams.

KEY RESPONSIBILITIES:

• Define, implement, and verify DFT architectures and test features for complex SoCs and IP subsystems.
• Drive scan insertion, ATPG generation, and test methodology development to achieve aggressive quality and coverage targets.
• Develop and execute gate-level simulation strategies for ATPG pattern validation and test readiness.
• Analyze test coverage, diagnose coverage gaps, and drive improvements in test quality, manufacturability, and test cost reduction.
• Partner with design, verification, physical design, and product engineering teams to ensure successful DFT implementation throughout the development cycle.
• Support silicon bring-up, manufacturing test execution, failure analysis, and yield improvement activities.
• Contribute to the development and deployment of scalable DFT methodologies, automation solutions, and best practices across projects.
• Provide technical leadership, mentorship, and guidance to engineers across the organization.

PREFERRED EXPERIENCE:

• Strong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.
• Strong RTL design and integration experience using Verilog and SystemVerilog.
• Experience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.
• Deep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.
• Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
• Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.
• Experience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.
• Proven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.
• Familiarity with FPGA architectures and prototyping methodologies is a plus.
• Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.
• Demonstrated ability to independently drive technical initiatives and solve complex engineering challenges.
• Excellent written and verbal communication skills, with the ability to effectively collaborate across geographically distributed teams.
• Proven ability to mentor engineers and contribute to technical leadership within an organization.

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

LOCATION:

San Jose, CA (Hybrid)